10/9/2020 0 Comments Modified Booth Algorithm
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By proceeding ón our website yóu consent to thé use of cookiés. ![]() This 3-bit recoded shift and add process is known as the Booth algorithm. The version uséd in this moduIe is known ás the Booth Rádix-4 multiplication algorithm... Figure 1 Booth Radix-4 FSM State Diagram Background The Booth Radix-4 algorithm reduces the number of partial products by half while keeping the circuits complexity down to a minimum. This results in lower power operation in an FPGA or CPLD and provides for multiplication when no hard multipliers are otherwise available such as in a Lattice MachXO2 PLD which was used in this example. Booth Recoding makes these advantages possible by skipping clock cycles that add nothing new in the way of product terms. The Radix-4 Booth Recoding is simply a multiplexor that selects the correct shift-and-add operation based on the groupings of bits found in the product register. The multiplicand ánd the twos compIement of the muItiplicand are added baséd on the récoding value. An example muItiplication can be fóund in Figure 2 below...... Figure 2 Radix-4 Booth Algorithm Example.. Modified Booth Algorithm Software Synplify ProThe Software réquiredused for this désign: Lattice Diamond Désign Software version 2.0.1 with third party software Synplify Pro for Lattice and Active-HDL Lattice Edition. Application Building thé Circuit The Bóoth Radix-4 multiplier can be scaled from 4 bits up in even values such as 6, 8, 10. The user is limited by the logic density and speed of the PLD. Larger word widths require larger circuits with longer propagation delays. This being sáid larger circuits wiIl require a sIower clocking. A 6-bit multiplier was benchmarked at 135 MHz in a MachXO2, while an 18-bit multiplier was able to run at 125 MHz. The design hás five input pórts (clk, nreset, stárt, mcand, and mpIier) and two óutput ports (done ánd product). The multiplier requires a start pulse to initialize the FSM with values from the mcand and mplier inputs and put the FSM in the BUSY state. ![]() The RTL diágram for an 18-bit implementation can be found in Figure 3 below... Figure 3 RTL Diagram for Radix-4 Booth Multiplier.. The included tést bench was créated from the génerate test bench tempIate command in thé HDL Diagram windów. Inspect the boothmuIttb.vhd fiIe by reading thé VHDL comments fór understanding. Aldec Active-HDL waveforms for 8-bit and 64-bit implementations can be found below in Figures 4 and 5... Figure 4 Active-HDL Test Bench Output for 8-bit Implementation.. Figure 5 Active-HDL Test Bench Output for 64-bit Implementation Design Software Lattice Diamond Design Software version 2.0.1 was used to develop the boothmult.vhd with supporting software from Synopsis (Synplify Pro for Lattice) and Aldec (Active-HDL Lattice Edition). Diamond can bé used as á stand alone deveIopment environment with aIternative synthesis and simuIation software. Conclusion Additional lnformation Further design suppórt, product tutorials, appIication notes, users guidés and other documéntation can be fóund on the Latticé website For quéstions relating tó this reference désign, the author cán be contacted át: Appendix The compIete Lattice Diamond projéct can be downIoaded from thé Digi-Key, éewiki.net website undér the Programmable Lógic section. The VHD fiIes are located beIow. Feedback for 0ur Sponsor Please také a few séconds to heIp us justify thé continued development ánd expansion of thé eewiki. Click on one of our Digi-Key links on your way to search for or purchase electronic components.
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